The present invention relates to semiconductor devices and fabrication of semiconductor devices, and more particularly, to semiconductor devices with transistors and related fabrication techniques.
A transistor can be formed on a semiconductor substrate to include a source region and a drain region defined in a well within the semiconductor substrate, and a gate electrode on a channel region between the source and drain regions. During operation, a well bias can be applied to the well, to increase the operational stability of the transistor. As integration densities increase, semiconductor device features continue to decrease and, consequently, the size of well pick up regions that can be used to apply well bias also continue to decrease.
FIG. 1 is a sectional view of conventional transistors with a structure that can be used to apply well bias. Referring to FIG. 1, a well 2 is formed in a semiconductor substrate 1, and a device isolating layer 3 is formed on the semiconductor substrate 1 to define active regions. A gate oxide layer 4 and a gate electrode 5 are sequentially formed on the active region. Dopant ions are implanted into the active regions adjacent to both sides of the gate electrode 5 to form source/drain regions 6. The source/drain regions 6 are formed in the well 2 and are doped with different type dopants from that in the well 2. A transistor is formed from a gate electrode 5 and associated source/drain regions 6. As shown in FIG. 1, a plurality of transistors are formed on the well 2.
A single well pick up region 7 is formed in the well 2. The single well pickup region 7 is shared by the plurality of transistors shown in FIG. 1. A well bias voltage is applied through the well pick up region 7 to the well 2 below the plurality of transistors.
One potential drawback of this structure is that although a sufficient level of well bias may be applied to a portion of the well 2 that is below the transistor immediately adjacent to the well pick up region 7 (e.g., leftmost side of the FIG. 1), an insufficient level of well bias may be applied to a portion of the well 2 that is below the transistor further from the well pick up region 7 (e.g., rightmost side of the FIG. 1). More particularly, as the distance between a portion of the well 2 that is below a transistor and the well pick up region 7 increases, the cumulative resistance between that portion of the well 2 and the well pick up region 7 correspondingly increases. As a result, the well voltage below transistors which are spaced relatively far from the well pick up region 7 can become insufficient to maintain stable operation of those transistors, and can result in latch-up and/or deterioration in noise margin for those transistors.